By Ann Steffora Mutschler
With PCB circuits running at very fast speeds today, the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with specific physical layout requirements that are not obvious. There are unexpected challenges, important high-speed considerations and efficient ways to account for them in high-speed PCB layouts.
Depending on who you are in the process of high-speed design, the message is somewhat different, said David Wiens, business development manager in the systems design division at Mentor Graphics. “The engineers design a product and wonder why the layout guys can’t build it. The layout guys wonder why everybody is beating up on them because it’s not just the engineering guys, it’s the mechanical guys, it’s the manufacturing guys all trying to push them for constraints.”
In the past, engineers were only dealing with 5% to 10% of nets being high-speed, but when that number jumps to 80%, a new approach must be taken. Analysis must be used very early on to set constraints, and then used again at the end of the process to validate the design. It’s becoming, to the extent where analysis as a virtual prototyping process, as simple and straightforward as designing a schematic and then designing a layout, he said.
According to Mentor data, year on year, from 2010 to 2011, designs shrunk 8% in terms of board area and board layers, but design density increased 30%. “The high was 80% for number of nets that were designed for high speed,” Wiens said. “It used to be 5% to 10%. Couple that with the maximum number of nets, which was 145,000. If you have 145,000 connections that you’ve got to make, of which 80% are high-speed, you can see the challenge in terms of the engineer having to analyze those, set up constraints in the design process that the layout guy can then use and then validating them at the back end.”
The key to this problem is collaboration. Engineers have to collaborate with layout designers throughout the process.
“They can’t just design something and then hope it works,” said Wiens. “That’s what we see as far as design practice. We see them working concurrently. Engineers are more familiar with the layout and the constraints used for it; layout guys are becoming more familiar with what those constraints actually mean. In a lot of cases the layout designers have to make compromises and tradeoffs just because they’re getting constraints from all over the place.”
A significant change from an electrical design perspective is when design engineers are creating topologies for a lower-speed DDR or a PCI bus, which are parallel interfaces and tend to run at lower speeds, according to Steven McKinney, market development manager for analysis products at Mentor Graphics. “Most of the time in those parallel interfaces you’re concerned about the clocks and how they are routed relative to data and address and those types of signals. It’s all about timing.”
However, with the move to SerDes architectures—PCI Express and the like—engineering teams no longer have to deal with timing so the design constraints are different. “Now you’re looking at loss budgets and how much of the signal is being attenuated as it goes across the printed circuit board, across a backplane or through a connector. The design criteria is shifting in terms of the things engineers have to be concerned with as they move from the slower parallel interfaces into the serial ones,” he said.
“Specifically for DDR3, and going forward in DDR4, these signals are running at very fast SerDes-type speeds, but they are wide parallel interfaces. They have a lot of timing constraints that have to be met. It’s one of the most challenging interfaces that people have to design for today because the speeds at which it’s operating lend it to be similar to SerDes, where you have to be thinking about loss and things like that for signal quality. You also have to deal with the old style of timing, where you have set up and hold timing and a bunch of tricks that happen on the actual silicon in order to make sure timing is met or to help you achieve timing. That’s a pretty significant shift in the technology in the architectures and interfaces on the PCB at a very high level,” McKinney continued.
Fig. 1. Eye density plot. Source: Mentor Graphics
Then, from an IP perspective, especially for high-speed SerDes, which are now running at 8 to 10 Gb per second, customers would like to get some kind of model from the IP vendor that helps them build up their PC board, according to Navraj Nandra, senior director of marketing, DesignWare Analog and MSIP solutions at Synopsys.
To help engineers model their system, Synopsys is providing IBIS-AMI (I/O Buffer Information Specification-Algorithmic Modeling Interface) models to allow users to utilize signal integrity modeling tools. “The model that we have describes quite accurately all the things that may impact board layout. These models are written in a way that you don’t spend hours and hours waiting for the simulation to complete because that can be a bit of a challenge if it’s like a low-level transistor model. From an inwardly-looking perspective we try and make sure that we’re minimizing the impact of signal integrity noise from our end,” Nandra said.
To this end, in the DDR PHY that users are running at 2133 Mbps, this is a single-ended interface, which is a big challenge from a noise and signal integrity aspect. To address these challenges, Synopsys, in the IP to ensure very high-speed signaling and to offset any of the problems on the PC board in the IP, has included things like per bit de-skewing. This concept is part of each DDR data lane and is trained at the power up.
“It’s an interesting concept because each board connects to memory interfaces differently. When the IP is in the system it actually has a training cycle on initiation when the IP is dialed up and it is maintained during the time that the chip is on so you get things like Vt drift and drift that can make the signal integrity or the skew worse, so in our IP we monitor that and maintain the drift,” he explained.
In addition, the company supplies low-jitter PLLs that are located very close to the pins that drive the clocks in order to help in reducing the skew on the PC board.
“We also use on-die termination (ODT),” Nandra said. “What that does is it actually does matching of the impedance of the board traces. It will match the impedance of the PC board traces with the IP such that you reduce the skew impact of the board in relation to the IP.”
Technology such as on-die decoupling capacitance will reduce jitter, which is coming out of the skew of the board and the signal integrity. “On-die decoupling really helps because the customer doesn’t actually see that capacitance, so the bill of materials from that perspective isn’t increasing because we’ve actually included it on the IP. That improves the jitter performance. It also reduces any kind of SSO (simultaneous switching output) effects. I actually see this firsthand. I was at a European customer last week and they are bringing up a set-top box and running a very high-speed DDR interface. We spent time talking about on-die termination and on-chip decoupling capacitance or on-die decoupling capacitance and how it helps to reduce jitter, SSO effects and all of the skews that they are getting on the PCB board. There’s so much you can model using various tools and then you’ve got to be a pretty smart board level engineer to know all of the problems that come up. If you try and solve as much as you can in the IP which alleviates anything that you can get downstream—that’s where we see our value as a supplier of IP,” he noted.
The big challenge with very high speed SerDes is the channel can have a big influence on the performance and these are not defined by any standards. Over the years, Synopsys accumulated close to 100 channel models that are described initially in some kind of 3D field solver simulation software, which converts it into an HSPICE model. Those are part of the company’s verification of the IP.
Additional resources:
Are Complex PCB Layout Topologies Slowing You Down?
Advanced PCI Express Design: Validating PCIe Channel Performance